Research project

FPGA Deployment of AI for Science and Engineering

Neural Electromagnetic Models for Electrical Machines

Coordinate-based neural networks can reproduce the magnetic field inside an electrical machine at any point, rotor position and operating condition. This project asks whether such models can run on embedded FPGA hardware without losing the accuracy of the engineering quantities derived from them: flux density, torque, torque ripple, stored energy and iron loss.

Research approach Hardware justification
  • Existing modelling frameworks and software inference pipeline
  • Proposed FPGA implementation, onboard benchmarks and HIL demonstrator
Illustration of a four-pole electrical machine cross-section with 36 stator slots; teal flux lines circulate between rotor poles and the stator yoke, and scattered dots mark arbitrary points where a neural field model can be queried.
Illustration. Flux lines come from a synthetic analytic potential, not from a simulation. The dots show arbitrary query points, because a coordinate-based model is a function, not a mesh.

Research motivation

From accurate desktop models to validated embedded deployment

Finite-element (FE) analysis is the reference method for the electromagnetic design of electrical machines, but a nonlinear FE solution at each rotor position is too slow for interactive design exploration, and far too slow for use alongside a running machine. Neural field models trained on FE data can reproduce the field at a fraction of the cost, and they already do so on desktop GPUs and CPUs.

Embedded execution is a different problem. Engineering quantities are not read directly from the network output. They are derived from it, and the derivation can amplify small errors:

  • Spatial differentiation. Flux density is the curl of the predicted vector potential, B = ∇ × (Az ẑ), so error in the gradient of the model output matters more than error in the output itself.
  • Angular finite differences. Torque from co-energy or virtual work differentiates with respect to rotor position. Torque ripple is a small difference between large values.
  • Harmonic loss calculations. Iron-loss models weight higher field harmonics more strongly, so quantisation noise that is negligible in Az can become significant in loss.

Arithmetic precision chosen for throughput on generic benchmarks may therefore break the physics. No established method yet links the number format of an embedded inference engine to the accuracy of machine-level quantities. This project aims to build that link, evaluate it on hardware, and connect it to measured machine operating conditions.

Research themes

Three questions, one demonstrator

AI for Science

Physics-aware learning of electromagnetic fields. The project validates physical consistency, not only pointwise error. Does the learned Az respect boundary conditions and periodicity, give physically plausible flux density at material interfaces, and stay consistent as the rotor moves?

AI for Engineering

Engineering quantities are the metric that matters: flux density, electromagnetic torque, torque ripple, stored magnetic energy and iron losses. Every model and every number format is judged by how well it reproduces these quantities relative to the FE reference.

AI Deployment

Custom mixed-precision arithmetic, streaming inference over large point sets, on-chip memory organisation for weights and activations, and embedded execution on an MPSoC. The aim is to understand the accuracy–resource–latency trade-off, not only to make inference fast.

Cross-cutting theme

Embedded digital twins and hardware-in-the-loop

Model predictions are connected to the measured operating conditions of a machine, such as currents and rotor position, acquired through additional mezzanine hardware. The demonstrator then evaluates whether field-level predictions can be produced alongside a machine at rates suited to monitoring and control studies. Real-time suitability is a question for this project to answer, not an assumption.

Proposed

Existing foundation

Two research frameworks already in place

The project starts from existing, working research software. Both repositories are currently private research code.

HairpinFE

Existing

Finite-element modelling and electromagnetic postprocessing

A modular two-dimensional finite-element package for rotating electrical machines. It builds the geometry from parameters, meshes it, solves the nonlinear magnetostatic or transient field, and rotates the rotor on a moving band. From the solution it computes torque, losses, inductances and related quantities.

In this project HairpinFE provides the reference data for training and the reference postprocessing against which embedded results are judged.

Repository: private research code

Hairpin_AI

Existing

Neural electromagnetic field modelling

A PyTorch framework of coordinate-based neural field models. Each model takes one row (machine design parameters, operating condition, rotor position, and spatial coordinates) and returns the magnetic vector potential Az at that point. Because the model is a function rather than a grid, it can be evaluated on the FE mesh, on a finer grid, or at a single sensor location.

Relevant architectures include residual MLPs with Fourier coordinate encoding and GELU activations, with optional rotor-frame features. A versioned input–output schema is stored with every checkpoint, so a separate inference engine can rebuild the model exactly.

Repository: private research code

Schematic of the neural field model: a query row of design parameters, operating point, rotor position and coordinates passes through a Fourier encoding and optional rotor-frame features, then a stack of residual blocks (Linear, GELU, Linear, with skip connection), producing Az at the queried point.
Schematic of the existing coordinate-based model family (not to scale). The residual multiply–accumulate stack is the main candidate for FPGA acceleration.

Technical approach

From finite-element reference to hardware-in-the-loop

Each stage is checked against the stage before it, so any loss of accuracy can be traced to a specific step: training, number format, hardware mapping, or measurement.

  1. 1

    FE reference data

    HairpinFE solutions across designs, operating points and rotor positions.

    Existing
  2. 2

    Neural model

    Coordinate-based Az models trained in Hairpin_AI on existing compute.

    Existing
  3. 3

    Precision evaluation

    Bit-accurate emulation of fixed-point and mixed-precision formats, scored on derived quantities.

    Proposed
  4. 4

    FPGA inference

    Streaming accelerator in programmable logic, using the formats selected in stage 3.

    Proposed
  5. 5

    EM postprocessing

    Flux density, torque, energy and loss, partitioned between Arm cores and logic.

    Proposed
  6. 6

    HIL validation

    Predictions driven by measured currents and rotor position via mezzanine hardware.

    Proposed

Precision is chosen by the physics

Number formats are selected per layer by measuring their effect on B, torque, ripple, energy and loss against the FE reference, not by output mean-squared error alone. A bit-accurate software emulator of the hardware arithmetic lets this search run before any logic is built, and later confirms that hardware output matches the emulator bit for bit.

Derivatives are handled explicitly

Because flux density needs spatial derivatives of Az, the project compares two routes: differentiating the network analytically, which needs extra datapath, and finite differences on the evaluated field, which amplify quantisation noise. The comparison is a research output in its own right.

Target hardware and justification

One AMD ZCU102 Zynq UltraScale+ MPSoC Evaluation Kit

The integrated research demonstrator is planned around this board. The features relied on and the reasons for the choice are set out below.

Verified board features

Device
Zynq UltraScale+ XCZU9EG-2FFVB1156E MPSoC
DSP slices
2,520
Logic cells
599,550
Block RAM
32.1 Mb total
Processing system
Quad-core Arm Cortex-A53 (APU); dual-core Arm Cortex-R5 (RPU); Mali-400 MP2 GPU
Memory
PS-side DDR4 64-bit SODIMM; PL-side DDR4 component memory (16-bit)
Expansion
Two VITA 57.1 FMC HPC connectors. HPC0 (J5) provides the full LA bus. HPC1 (J4) implements a subset, LA[00:29]. Mezzanine compatibility must be checked against the board pinout.

Source: AMD, ZCU102 Evaluation Board User Guide, UG1182 (v1.7), 21 February 2023 [1].

Why this board

  1. Precision that preserves engineering quantities. Scientific field prediction may need wider fixed-point or mixed-precision formats in selected layers than inference tuned for classification. Wider multipliers consume more DSP slices per operation, so DSP capacity sets how far the precision study can explore while keeping a useful level of parallelism.
  2. More than inference on one chip. The demonstrator combines the inference engine with field reconstruction, derivative evaluation, buffering of point sets and rotor-position sequences, and acquisition logic. The ZU9EG's programmable logic and on-chip memory leave room for these blocks together.
  3. Processor–logic partitioning is a research objective. Deciding which postprocessing steps belong on the Cortex-A53 cores and which belong in logic is part of the study. The MPSoC lets both options be measured on the same device.
  4. A route to hardware-in-the-loop. The FMC HPC connectors accept compatible ADC and motor- or sensor-interface mezzanine cards. These cards are additional hardware, not built-in ZCU102 capabilities, and connector routing limitations will be checked before any card is selected.

Proposed hardware–software architecture

ZCU102 · XCZU9EG MPSoC

Processing system Arm Cortex-A53 × 4

  • Configuration and model loading (weights and input–output schema)
  • Communication with the host and experiment control
  • Selected postprocessing, e.g. torque integration and loss summation
  • Benchmark logging: latency, energy, accuracy

Programmable logic DSP · BRAM · fabric

  • Streaming inference engine for the residual MLP
  • Fourier coordinate encoding
  • Selected field-processing kernels, e.g. flux-density reconstruction
  • Acquisition interface and sample buffering
PS DDR4 (SODIMM) · PL DDR4: weights, point sets, result buffers

Host workstation

Training (existing resources), FE reference, analysis

FMC mezzanine cards Additional hardware

Compatible ADC and motor/sensor interface for HIL

Proposed partitioning (schematic). Training stays on the existing computing resources, and only inference and selected postprocessing move to the board. The final split between processor and logic is a research outcome.

Validation

What will be measured

The project will report all four dimensions together, because a gain in one is meaningful only when the others are stated. No hardware results exist yet. The figures below are planned measurements, not claims.

Physical accuracy

Error in Az, flux density, torque and ripple, stored energy and iron loss relative to HairpinFE, for software floating point, the bit-accurate emulator and on-board output.

Latency

Time per point, per field map and per rotor-position sequence, end to end and per stage, compared with the existing CPU/GPU software pipeline.

Energy consumption

Board-level energy per field evaluation, using on-board power monitoring where available and external measurement where needed. Method and uncertainty will be reported.

Resource utilisation

DSP, LUT, flip-flop and block RAM use per design point, linking each precision choice to its hardware cost.

Proposed 12-month roadmap

Work plan

  1. Months 1–3

    Reference benchmarks and precision evaluation

    Fix benchmark machines, operating points and FE references. Build the bit-accurate arithmetic emulator. Map how precision affects every derived quantity.

  2. Months 4–6

    Inference accelerator and software integration

    Implement the streaming inference engine in programmable logic. Integrate it with Linux on the Cortex-A53 cores and verify it bit for bit against the emulator.

  3. Months 7–9

    Physical validation and postprocessing acceleration

    Validate on-board predictions against FE references. Accelerate selected postprocessing kernels and evaluate partitioning options between processor and logic.

  4. Months 10–12

    Hardware benchmarks, documentation and dissemination

    Run the full benchmark campaign on accuracy, latency, energy and resources. Document the demonstrator, release benchmark material where permitted, and prepare publications.

Expected outputs

What the project will deliver

Research demonstrator

A ZCU102-based system running neural electromagnetic field inference with selected postprocessing, extended towards hardware-in-the-loop operation with measured machine conditions.

Reproducible benchmarks

Defined benchmark cases, FE references and measurement procedures, so that accuracy, latency, energy and resource results can be reproduced and compared.

Deployment guidance

Practical guidance on choosing number formats, memory organisation and processor–logic partitioning for scientific neural field models, where derived quantities rather than labels define success.

Technical references

References

  1. AMD (Xilinx), ZCU102 Evaluation Board User Guide, UG1182 (v1.7), Feb. 2023. PDF
  2. M. Tancik et al., “Fourier features let networks learn high frequency functions in low dimensional domains,” in Proc. NeurIPS, 2020. arXiv:2006.10739
  3. K. He, X. Zhang, S. Ren and J. Sun, “Deep residual learning for image recognition,” in Proc. IEEE CVPR, 2016, pp. 770–778. doi:10.1109/CVPR.2016.90
  4. D. Hendrycks and K. Gimpel, “Gaussian error linear units (GELUs),” 2016. arXiv:1606.08415
  5. M. Raissi, P. Perdikaris and G. E. Karniadakis, “Physics-informed neural networks: A deep learning framework for solving forward and inverse problems involving nonlinear partial differential equations,” J. Comput. Phys., vol. 378, pp. 686–707, 2019. doi:10.1016/j.jcp.2018.10.045
  6. A. Arkkio, “Analysis of induction motors based on the numerical solution of the magnetic field and circuit equations,” Acta Polytechnica Scandinavica, Electrical Engineering Series, no. 59, 1987.
  7. G. Bertotti, “General properties of power losses in soft ferromagnetic materials,” IEEE Trans. Magn., vol. 24, no. 1, pp. 621–630, 1988. doi:10.1109/20.43994
  8. B. Jacob et al., “Quantization and training of neural networks for efficient integer-arithmetic-only inference,” in Proc. IEEE CVPR, 2018, pp. 2704–2713. arXiv:1712.05877
  9. Y. Umuroglu et al., “FINN: A framework for fast, scalable binarized neural network inference,” in Proc. ACM/SIGDA FPGA, 2017, pp. 65–74. arXiv:1612.07119
  10. J. Duarte et al., “Fast inference of deep neural networks in FPGAs for particle physics,” J. Instrum., vol. 13, P07027, 2018. arXiv:1804.06913